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Other registers

Interrupt Control and State Register

The ICSR is used to:

  • Set to pending state, read pending state, or clear pending state of NMI, SVCall or SysTick.
  • Control the security state of SysTick if a single SysTick is implemented with the Secure Extension.
  • Indicate whether a pending exception is serviced on exit from Debug halt state (ISRPREEMPT).
  • Indicate whether an external interrupt is pending (ISRPENDING).
  • Indicate the exception number of the highest priority pending exception.
  • Indicate whether there is only one active exception (RETTOBASE).
  • Indicate the current active exception (same as IPSR).
  • Set NMI to pending state.
  • Indicate whether NMI is pending when in Debug state (ISRPENDING).
  • Indicate whether a pending exception is serviced on exit from Debug halt state (ISRPREEMPT).
  • Set and clear PENDSV and SysTick.
  • Indicate the current active exception (same as IPSR)
icsr_bits.png

Configuration and Control register

control_bits.png

Bit value

Identifier

Description

[18] BP Branch prediction enable.
[17] IC Instruction cache enable.
[16] DC Data cache enable.

[10]

STKOFHFNMIGN

Determines the effect of stack overflow on HardFault and NMI handlers.

[8]

BFHFNMIGN

Determines the effect of synchronous data access faults on HardFault and NMI handlers.

[4]

DIV_0_TRP

Controls the trap for Divide by zero.

[3]

UNALIGN_TRP

Controls the trap of unaligned word and halfword accesses.

[1]

USERSETMPEND

Controls whether unprivileged software can access the Software Triggered Interrupt Register (STIR) which provides a mechanism for software to trigger an interrupt.

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