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Special purpose mask registers

The exception mask registers disable the handling of exceptions by the processor. An example of the use of these registers would be to disable exceptions when they might affect timing critical tasks.

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All exception mask registers can be modified using MRS and MSR instructions. PRIMASK and FAULTMASK can also be accessed using the CPS instruction.

The behavior differs depending on whether ARMv8-M architecture with Security Extension is implemented or not. All exceptions have an associated priority, with a low value indicating a high priority. Low priority exceptions take precedence.

Priority Mask Register

The PRIMASK register prevents servicing of all exceptions with configurable priority. Setting PRIMASK to 1 raises the execution priority to 0.

Fault Mask Register (only with ARMv8-M architecture with Main Extension)

The FAULTMASK register prevents servicing of all exceptions except Non-maskable Interrupts, HardFaults, or Resets.

Setting FAULTMASK to 1 raises the execution priority to -1, the priority of HardFault. Only privileged software executing at a priority below -1 can set FAULTMASK to 1. This means HardFault and NMI handlers cannot set FAULTMASK to 1. Returning from any exception except NMI clears FAULTMASK to 0.

PRIMASK and FAULTMASK map to the I and F flags.

CPSID I  ; set PRIMASK (disable interrupts)

CPSIE I  ; clear PRIMASK (enable interrupts)

CPSID F  ; set FAULTMASK (disable faults and interrupts)

CPSIE F  ; clear FAULTMASK (enable faults and interrupts)

Base Priority Mask Register (only with ARMv8-M architecture with Main Extension)

BASEPRI changes the priority level required for exception preemption. It has an effect only when BASEPRI has a lower value than the unmasked priority level of the currently executing software.

The number of implemented bits in BASEPRI is the same as the number of implemented bits in each field of the priority registers, and BASEPRI has the same format as those fields. A value of zero disables masking by BASEPRI.

When BASEPRI is set to a nonzero value, it prevents the servicing of all exceptions with the same or lower group priority level as the BASEPRI value.

BASEPRI is accessed like a Program Status Register

MSR{cond} BASEPRI, Rm      ; write BASEPRI

MRS{cond} Rd, BASEPRI      ; read BASEPRI

Alternatively, you can use the following CMSIS functions:

PRIMASK: __enable_irq(), __disable_irq()

FAULTMASK: __enable_fiq(), __disable_fiq()

BASEPRI: __get_BASEPRI(), __set_BASEPRI(uint32_t value)

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