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System security controller

The system security controller is a peripheral component accessible only by Secure transactions. The controller holds all the register fields that are used to modify the configurable aspects of the system security. For example, for a full Implementation Defined Attribution Unit (IDAU), whether an address region is NSC, which peripherals are accessible by NS transactions, and where the boundary between Secure and Non-secure memory is in RAM.

The system security controller might include logic for monitoring violations that are detected by the security gates, and consolidating any events into a Secure interrupt, that targets a Secure processor within the system.

The peripheral register map and bit assignments are not described further. All references to control here imply the existence of an associated software modifiable field within the system security controller.

In addition to only being accessible by Secure software, the system security controller can also be locked. For example, when Secure software has programmed the controller, it can be locked to prevent further accidental modification until the system is reset.

The system security controller shares some similarities with existing power and clock controllers found in microcontrollers (MCUs), and as such inclusion of this functionality in the same or neighboring block might make sense.

Note:

The number and location of system security controllers is left to the implementer.
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