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Why Should the Two Lowest Interrupt Priorities be Reserved for the Secure OS in Armv8-M Processors?

Article ID: 165521431

Published date: 13 Feb 2018

Last updated: -

Applies to: M-profile


Why should the two lowest interrupt priorities be reserved for the Secure OS in Armv8-M Processors?




In Arm Cortex-M processors, the Real Time Operating System (RTOS) uses the PendSV exception for context switching. Interrupt handlers might request context switching, and nested interrupt handlers might repetitively request context switching. Therefore, the PendSV exception must have the lowest priority to ensure that the context is switched only once.

In Armv8-M processors, exceptions can be handled in Secure state and Non-secure state. Exceptions handled in Secure state are known as Secure exceptions, while exceptions handled in Non-secure state are known as Non-secure exceptions.

In terms of exception priority, you can set the AICR_S.PRIS bit to force the priorities of Non-secure exceptions into the lower half of the priority range. The actual priories of Non-secure exceptions are calculated by using the following equation:

PRINS = (PRINS >> 1) + 0x80 ; When AICR_S.PRIS == 1

When a Secure OS is implemented in a Secure domain, the PendSV exception is assigned with the lowest priority, for example 0xFF. If the priority of a Non-secure interrupt is one of the lowest two priorities, for example 0xFE or 0xFF, the final priority is the same as the priority of PendSV in the Secure domain. In addition, if the exception number of PendSV (14) is smaller than the exception number of interrupts (which is equal to or greater than 16), the PendSV exception can preempt the interrupt and break the context switching rule described above.

Note: The number of priority bits implemented by an Armv8-M processor might be smaller than 8, so the value of the two lowest priorities can be different. See the device specification for details.





Related Information

  • Armv8-M Architecture Reference Manual