The interface module provides two A to D Converters (ADC) and a D to A Converter (DAC). The two ADCs each provide eight analog inputs with buffered 0-5V inputs, an internal multiplexer, and a 12-bit converter. The ADCs provide a 16-bit host interface with conversion data appearing on D[11:0] (and zeros on D[15:12]). The ADCs are clocked by a 4MHz crystal and are able to perform 200ksamples/s.
The DAC provides two 0-5V outputs with a 12-bit resolution.
The ADCs and DAC are powered from a 5V supply and share buffers to interface them to the 3.3V system bus provided by the logic module.
Figure 3.10 shows the architecture of the ADCs and DACs.
All of the interface signals are routed to the FPGA on the logic module. The ADCs and DAC are supported by an AHB interface that is instantiated in the logic module code example supplied with the IM-AD1.
Table 3.10 shows the assignment of the ADC and DAC interface signals to the logic module signals on the EXPIM connector.
|AD_D[15:0]||IM_ABANK[47:32]||ADC and DAC data bus|
|AD_T/R||IM_ABANK48||Buffer direction control|
|AD_nOE||IM_ABANK49||Buffer output enable|
|ADC1_nCONV||IM_ABANK50||ADC1 conversion start signal|
|ADC1_nCS||IM_ABANK51||ADC1 chip select|
|ADC1_nWR||IM_ABANK52||ADC1 write strobe|
|ADC1_nRD||IM_ABANK53||ADC1 read strobe|
|ADC2_nCONV||IM_ABANK54||ADC2 conversion start signal|
|ADC2_nCS||IM_ABANK55||ADC2 chip select|
|ADC2_nWR||IM_ABANK56||ADC2 write strobe|
|ADC2_nRD||IM_ABANK57||ADC2 read strobe|
|DAC_nLDAC||IM_BBANK50||DAC load signal|
|DAC_A0||IM_BBANK51||DAC address bit|
|DAC_nCS||IM_BBANK52||DAC chip select|
|DAC_nWR||IM_BBANK53||DAC write strobe|
The ADCs are clocked from a 4MHz oscillator. This also supplies the IM_CLK signal routed to the logic module FPGA. This is used in the example logic to clock the DC-DC converter PrimeCell peripheral and the stepper motor interfaces.
The analog inputs to the ADCs are buffered by LMV324 operational amplifiers (op-amps). The op-amps are configured to give unity gain but the inputs have a resistive divider that divides the input voltage by 2. A 0-5V input signal range at the buffer inputs provides a 0-2.5V full range at the ADC input. If different input ranges are required the divider resistor values can be changed.
The op-amp buffers cannot drive their outputs lower than 65mV. This means input signals less than 130mV will have incorrect ADC values.
The reference voltage from one of the ADCs is buffered and fed to the reference inputs of the other ADC and the DAC so that all devices share a common reference. The GAIN input to the DAC is tied HIGH to configure the output range of the DAC to be 0 to 2xVref.
Figure 3.11 shows the pinout of the ADC interface connector (J1).
Figure 3.12 shows the pinout of the DAC interface connector (J2).