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4.2.4. PLD image selection

When the core module is powered ON or reset, the ARM core loads a configuration image into the PLD from the flash memory at EBI0 (see Flash memory). This operation is controlled by some initialization code that resides in the bottom of each configuration image stored in flash.

The core module is supplied with four images already programmed into the flash. You can also download your own images into the flash by setting S1[4] to ON or by fitting the CONFIG link, see Loading new PLD configurations.

To select an image, set the mode switch S1 or use the signals CFGSEL[1:0] from a motherboard. These generate the address bits CFG_EBI_A[22:21] that are used to select the required configuration image. Figure 4.4 shows the PLD configuration architecture on the core module.

Figure 4.4. PLD configuration architecture

Figure 4.4. PLD configuration architecture

Note

The switch elements on S1 are engraved 1, 2, 3, and 4. These align with the signals CFG_nSW0, CFG_nSW1, CFG_nSW2, and CFG_nSW3 respectively.

When to use the mode switch for image selection

Use the switches if you have written your own configuration image into the flash to ensure that the correct image is selected for your design. Table 4.2 shows the mode switch settings required to select the images. To use S1[1] a nd S1[2] for image selection, set S1[3] to ON.

Image selection using the mode switch
S1[4]S1[3]S1[2]S1[1]Image IDMeaning with the supplied images
OFFONOFFOFF11The core module can be used with an Integrator/CP baseboard.
OFFON10The core module can be used standalone or with an Integrator/AP.
ONOFF01The core module can be used with an Integrator/IM-PD1.
ONON00This selects the basic example image.

When to use CFGSEL[1:0] for image selection

The signals CFGSEL[1:0] are static signals used by different Integrator motherboards as a type identifier. They are used to select the image that enables the core module to be used with that motherboard. Use this option, if you mount the core module on an Integrator/AP or CP and are using the PLD images in the locations supplied.

The meaning of the CFGSEL[1:0] values settings is given in Table 4.3. To use CFGSEL[1:0] signals for image selection, set S1[3] to OFF.

Image selection using CFGSEL[1:0]
S1[4]S1[3]S1[2]S1[1]CFGSEL[1:0]Meaning with supplied images
OFFOFFxx00Image 00 is selected. This code is not generated by any of the currently available Integrator boards.
01Image 01 is selected. This code is not generated by any currently available Integrator boards.
10Image 10 is selected. This is the default. This code is generated by pullup and pulldown resistors on CFGSEL[1:0] on the core module or by an Integrator/AP motherboard. Use an image that enables the core module to be used standalone or with an Integrator/AP.
11Image 11 is selected. This code is generated by an Integrator/CP baseboard. Use an image that enables the core module to be used with an Integrator/CP baseboard.
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