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4.2.2. Stripe memory and peripherals

The stripe internal components are shown in Figure 4.3 and include:

  • memory:

    • 256KB SRAM

    • 128KB Dual port RAM.

  • peripherals:

    • Interrupt controller

    • UART

    • timer

    • watchdog timer.

  • SDRAM controller for off-chip SDRAM

  • Expansion Bus Interface (EBI)

  • reset controller

  • Phase Locked Loop (PLL)

  • AHB master and slave bridges to the PLD

  • configuration logic.

These devices and their control registers are described in the Excalibur ARM-Based Embedded Processor PLD Hardware Reference Manual.

Figure 4.3. Embedded processor stripe internal architecture

Figure 4.3. Embedded processor stripe internal
architecture

These functional blocks within the stripe enable the core, independently of the PLD configuration, to carry out the following functions:

  • access external boot memory

  • boot and run a program

  • program the PLD

  • run interactive debug

  • detect errors and restart, reboot, or reprogram the system as required

  • communicate with a terminal

  • run a real-time operating system.

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