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4.6. Core module clocks

The core module clocks are described in:

Figure 4.11 shows the clock generation architecture of the core module. The programmable clock outputs are generated by the two ICS307 devices, OSC1 (U13) and OSC2 (U15). U13 is supplied with a reference clock from a 24MHz crystal oscillator and provides a programmable reference clock to U15 (this is set to 24MHz by default). A second crystal supplies a 33MHz fixed frequency clock to the stripe.

The clock signals are buffered and then supplied to other modules in the system, to the PLD, and to the logic analyzer connectors as described in Table 4.8. The output enable of the buffer U12B is controlled by the signal MBDET so that these outputs are only enabled when the core module is used without a motherboard.

Figure 4.11. Clocking architecture

Figure 4.11. Clocking architecture
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