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4.5.2. Double Data Rate SDRAM

Four 32MB 16-bit Double Data Rate (DDR) SDRAM chips are fitted permanently on the core module. The data, address, refresh, and control signals for these are supplied by the SDRAM controller incorporated into the stripe. They are organized into two 32-bit banks each of 64MB. The base address of each memory bank is determined by configuration data loaded when the core module is powered ON. The supplied PLD images always map the DDR SRAM to 0x0.

Figure 4.9 shows a simplified block diagram of the DDR SDRAM.

Figure 4.9. DDR SDRAM block diagram

Figure 4.9. DDR SDRAM block diagram
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