A 2MB 32-bit SSRAM chip is fitted permanently to the core module. This uses signals from the user programmable PLD for data, address, and control signals. Some of the signals used are shared with the optional SDRAM DIMM, which means that they cannot both be used at the same time, see SSRAM and SDRAM DIMM interface signals.
The CP and IM-PD1 images implement an SSRAM controller. The SSRAM is used by the CP and IM-PD1 images as a frame buffer for the Color LCD Controller (CLDC) implemented in these images. However, the CM PLD image does not provide an SSRAM controller.