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4.5.5. SSRAM and SDRAM DIMM interface signals

Figure 4.10 shows the memory interface signal connections from the PLD to the SSRAM and DIMM socket.

Figure 4.10. PLD/memory interface signals

Figure 4.10. PLD/memory interface signals

The DIMM_DQ[63:0] signals are shared by the SSRAM and socket. The the SSRAM controllers in the CM and IM-PD1 images use the shared signals as shown in Table 4.7.

Assignment of DIMM_DQ signals to SSRAM
SignalsSSRAM assignment
DIMM_DQ[58:50]Control
DIMM_DQ[49:32]Address
DIMM_DQ[31:0]Data
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