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4.7. Reset architecture

The core module provides several reset signal inputs to and outputs from the PLD. The PLD images supplied with the core module incorporate a reset control logic block that enables the core module to be reset as a standalone unit or as part of a larger development system. The core module is designed to be reset from the following sources:

  • a Power On Reset (POR)

  • push button resets

  • resets received from a motherboard or other modules

  • resets from a Multi-ICE unit or ByteBlaster equipment

  • resets generated by software writing to a register within the PLD.

Figure 4.14 shows the architecture of the reset control subsystem.

Figure 4.14. Reset architecture

Figure 4.14. Reset architecture
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