Differentiate your design

Arm Custom Instructions open the door to implement bespoke data processing operations without introducing complexity to the software development flow. By using Arm Custom Instructions, silicon architects can differentiate the design without compromising quality, ease-of-use, and security.


Specifications and features

Arm Custom Instructions enable a new level of optimization to meet the increasing industry demand for workload specific compute. Arm Custom Instruction features are:

  • Arm architecture compliant
  • Supported by standard Arm compliant software development tools, including open-source compilers such as GCC
  • Tightly coupled to the processor pipeline, bringing the highest performance efficiency gains to latency and power-sensitive applications
  • Supported in hardware and software to ensure co-development between both teams
  • Compatible with TrustZone technology

Arm Custom Instructions for the Armv8-M architecture

Arm Custom Instructions for the Armv8-M architecture enable you to push performance and efficiency further by adding application domain specific features in small embedded processors, while maintaining all the advantages of Arm’s software ecosystem.

Arm Custom Instructions allow you to add a customizable module, called configuration space, inside the Cortex-M33 processor. This module is driven by the pre-decoded instructions and shares the same interface as the standard arithmetic logic unit (ALU) of the CPU. Adding custom instructions to a customizable CPU requires two steps:

  1. Providing a configuration file that lists the regions you want to use for adding your own custom instructions.
  2. Building the data path for your own custom instructions and integrating it into the configuration space.

The configuration space can implement one of the following Arm Custom Instruction formats, which are defined by the Arm Instruction Set Architecture:

Instruction Assembly
General-purpose registers and NZCV flags
CX1{A} CX1{A} Pn, {Rd,} Rd, #imm
CX2{A} CX2{A} Pn, {Rd,} Rd, Rn, #imm
CX3{A} CX3{A} Pn, {Rd,} Rd, Rn, Rm, #imm
CX1{A}.D CX1D{A} Pn,{Rd,} Rd, #imm
CX2{A}.D CX2D{A} Pn, {Rd,} Rd, Rn, #imm
CX3{A}.D CX3D{A} Pn, {Rd,} Rd, Rn, Rm, #imm
FPU/M-Profile Vector Extension (MVE) registers
VCX1{A}.F VCX1{A} Pn, {Sd,} Sd, #imm
VCX2{A}.F VCX2{A} Pn, {Sd,} Sd, Sn, #imm
VCX3{A}.F VCX3{A} Pn, {Sd,} Sd, Sn, Sm, #imm
VCX1{A}.D VCX1{A} Pn, {Dd,} Dd, #imm
VCX2{A}.D VCX2{A} Pn, {Dd,} Dd, Dn, #imm
VCX3{A}.D VCX3{A} Pn, {Dd,} Dd, Dn, Dm, #imm
VCX1{A}.Q VCX1{A} Pn, {Qd,} Qd, #imm
VCX2{A}.Q VCX2{A} Pn, {Qd,} Qd, Qn, #imm
VCX3{A}.Q VCX3{A} Pn, {Qd,} Qd, Qn, Qm, #imm

Arm Custom Instructions for Armv8-M

To see an example in practice and explore further details of the capabilities enabled for Arm Custom Instructions, download our white paper

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