Specification
Armv8-A and Armv8-R Architectures
This page describes floating-point support for Cortex-A and Cortex-R processors. For information on floating-point support for Cortex-M, please refer to the DSP for Cortex-M page.
The Armv8 architecture supports single-precision (32-bit) and double-precision (64-bit) floating-point data types and arithmetic as defined by the IEEE 754 floating-point standard. It also supports the half-precision (16-bit) floating-point data type for data storage, by supporting conversions between single-precision and half-precision data types and double-precision and half-precision data types. When Armv8.2-FP16 is implemented, it also supports the half-precision floating-point data type for data-processing operations.
The Advanced SIMD (NEON) instructions provide packed Single Instruction Multiple Data (SIMD) and single-element scalar operations, and support:
Single-precision and double-precision arithmetic in AArch64 state
Single-precision arithmetic only in the AArch32 state
When Armv8.2-FP16 is implemented, half-precision arithmetic is supported in AArch64 and AArch32 states
Floating-point support in AArch64 state SIMD is IEEE 754-2008 compliant with:
Configurable rounding modes
Configurable Default NaN behavior
Configurable Flush-to-zero behavior
Floating-point computation using AArch32 Advanced SIMD instructions remains unchanged from Armv7.
Scalable Vector Extension (SVE) for Armv8-A
SVE is the next-generation SIMD instruction set for AArch64 that introduces the architectural features for High-Performance Computing (HPC). SVE extends the floating-point capability of the Armv8-A architecture targeting A64 ISA only.
Armv7-A/R and previous architectures
Prior to Armv8-A/R, the Arm architecture distinguishes between scalar (VFP) and Advanced SIMD extension (NEON) floating-point support.
Up to Armv7-A/R architecture (included), floating-point architecture is a floating-point coprocessor extension to the instruction set architectures. For historical reasons, the floating-point extension is also called the VFP Extension.
VFPv1
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Obsolete. Details are available on request from Arm.
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VFPv2
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An optional extension to:
the Arm instruction set in the Armv5TE, Armv5TEJ, Armv6, and Armv6K architectures
the Arm and Thumb instruction sets in the Armv6T2 architecture
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VFPv3
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An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the Armv7-A and Armv7-R profiles. VFPv3 can be implemented with either 32 or 16 doubleword registers. VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support code.
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VFPv3 with Half-precision Extension
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VFPv3 and VFPv3U can be extended by the optional Half-precision Extension, that provides conversion functions in both directions between half-precision floating-point and single-precision floating-point.
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VFPv4
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An optional extension to the Arm, Thumb, and ThumbEE instruction sets in the Armv7-A and Armv7-R profiles. VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support code. VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to the features of VFPv3. VFPv4 can be implemented with either 32 or 16 doubleword registers.
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VFPv5
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The FPv5 FPU includes all the functionality of VFPv4 and adds optional double-precision floating-point arithmetic, conversions between integer, single-precision floating-point, double-precision floating-point and half-precision floating-point formats FPv5 also introduces new instructions. For more information refer to the Arm Architecture Reference Manual.
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The Armv7-A/R Advanced SIMD extension (NEON) offers single-precision floating-point support and performs IEEE 754 floating-point arithmetic with the following restrictions:
Denormalized numbers are flushed to zero
Only default NaNs are supported
The Round to Nearest rounding mode is used
Untrapped floating-point exception handling is used for all floating-point exceptions
For more detailed information, please refer to the Arm Architecture Reference Manual.