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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint64_t[__arm_]uqshll(uint64_t value, const int shift)Shift / Left / Vector saturating rounding shift left
Description
Unsigned saturating shift left by 1 to 32 bits of a 64 bit value stored in two general-purpose registers.
Results
[RdaHi,RdaLo] result
This intrinsic compiles to the following instructions:

UQSHLL RdaLo,RdaHi,#shift

Argument Preparation
value register: [RdaHi,RdaLo]shift minimum: 1; maximum: 32
Architectures
MVE