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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint32x4_t[__arm_]vadcq_m[_u32](uint32x4_t inactive, uint32x4_t a, uint32x4_t b, unsigned * carry, mve_pred16_t p)Vector arithmetic / Add / Addition
Description
Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the 'I' variant. FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.
Results
Qd resultRt *carry
This intrinsic compiles to the following instructions:

VMRS Rs,FPSCR_nzcvqc

BFI Rs,Rt,#29,#1

VMSR FPSCR_nzcvqc,Rs

VMSR P0,Rp

VPST

VADCT.I32 Qd,Qn,Qm

VMRS Rt,FPSCR_nzcvqc

LSR Rt,#29

AND Rt,#1

Argument Preparation
inactive register: Qda register: Qnb register: Qmcarry register: Rtp register: Rp
Architectures
MVE