[__arm_]vaddlvq_p[_u32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint64_t | [__arm_]vaddlvq_p[_u32] | (uint32x4_t a, mve_pred16_t p) | Vector arithmetic / Add / Addition | |
Description Add across the elements of a vector accumulating the result into a scalar. The 64 bit result is stored across two registers, the upper-half is stored in an odd-numbered register and the lower half is stored in an even-numbered register. The initial value of the general-purpose destination registers can optionally be added to the result. Results [RdaHi,RdaLo] result This intrinsic compiles to the following instructions: VMSR VPST VADDLVT.U32 Argument Preparation a register: Qmp register: Rp Architectures MVE | |||||
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