[__arm_]vbicq_m[_f16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float16x8_t | [__arm_]vbicq_m[_f16] | (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) | Bit manipulation / Bitwise clear | |
Description Compute a bitwise AND of a vector register and the complement of a vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VBICT Argument Preparation inactive register: Qda register: Qnb register: Qmp register: Rp Architectures MVE | |||||
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