SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumfloat16x8_t[__arm_]vbicq_m[_f16](float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)Bit manipulation / Bitwise clear
Description
Compute a bitwise AND of a vector register and the complement of a vector register.
Results
Qd result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VBICT Qd,Qn,Qm

Argument Preparation
inactive register: Qda register: Qnb register: Qmp register: Rp
Architectures
MVE