[__arm_]vclzq_m[_s32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int32x4_t | [__arm_]vclzq_m[_s32] | (int32x4_t inactive, int32x4_t a, mve_pred16_t p) | Bit manipulation / Count leading zeros | |
Description Count the leading zeros of each element in a vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VCLZT.I32 Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.