[__arm_]vclzq_x[_u8]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint8x16_t | [__arm_]vclzq_x[_u8] | (uint8x16_t a, mve_pred16_t p) | Bit manipulation / Count leading zeros | |
Description Count the leading zeros of each element in a vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VCLZT.I8 Argument Preparation a register: Qmp register: Rp Architectures MVE | |||||
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