SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliummve_pred16_t[__arm_]vcmpeqq_m[_n_f32](float32x4_t a, float32_t b, mve_pred16_t p)Compare / Equal to
Description
Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.
Results
Rd result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VCMPT.F32 eq,Qn,Rm

VMRS Rd,P0

Argument Preparation
a register: Qnb register: Rmp register: Rp
Architectures
MVE