[__arm_]vcmpleq[_n_f16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | mve_pred16_t | [__arm_]vcmpleq[_n_f16] | (float16x8_t a, float16_t b) | Compare / Less than or equal to | |
Description Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed. Results Rd result This intrinsic compiles to the following instructions: VCMP.F16 VMRS Argument Preparation a register: Qnb register: Rm Architectures MVE | |||||
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