SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliummve_pred16_t[__arm_]vcmpneq[_n_f32](float32x4_t a, float32_t b)Compare / Not equal to
Description
Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.
Results
Rd result
This intrinsic compiles to the following instructions:

VCMP.F32 ne,Qn,Rm

VMRS Rd,P0

Argument Preparation
a register: Qnb register: Rm
Architectures
MVE