[__arm_]vctp64q
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | mve_pred16_t | [__arm_]vctp64q | (uint32_t a) | Predication / Create vector tail predicate | |
Description Creates a predicate pattern in VPR.P0 such that any element numbered the value of Rn or greater is predicated. Any element numbered lower than the value of Rn is not predicated. If placed within a VPT block and a lane is predicated, the corresponding VPR.P0 pattern will also be predicated. The generated VPR.P0 pattern can be used by an ensuing predication instruction to apply tail predication on a vector register. Results Rd result This intrinsic compiles to the following instructions: VCTP.64 VMRS Argument Preparation a register: Rn Architectures MVE | |||||
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