[__arm_]vcvtq_x_u16_f16
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint16x8_t | [__arm_]vcvtq_x_u16_f16 | (float16x8_t a, mve_pred16_t p) | Data type conversion / Conversions | |
Description Convert each element in a vector from floating-point to integer using the specified rounding mode and place the results in a second vector. If a source element is outside the range of the target integer type, the result element is saturated. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VCVTT.U16.F16 Argument Preparation a register: Qmp register: Rp Architectures MVE | |||||
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