[__arm_]vcvttq_m_f32_f16
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float32x4_t | [__arm_]vcvttq_m_f32_f16 | (float32x4_t inactive, float16x8_t a, mve_pred16_t p) | Data type conversion / Conversions | |
Description Convert between half-precision and single-precision floating-point values in elements of a vector register. For half-precision to single-precision operation, the top half (T variant) or bottom half (B variant) of the source vector register is selected. For single-precision to half-precision operation, the top half (T variant) or bottom half (B variant) of the destination vector register is selected and the other half retains its previous value. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VCVTTT.F32.F16 Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
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