[__arm_]vdupq_m[_n_u32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint32x4_t | [__arm_]vdupq_m[_n_u32] | (uint32x4_t inactive, uint32_t a, mve_pred16_t p) | Vector manipulation / Create vector | |
Description Set each element of a vector register to the value of a general-purpose register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VDUPT.32 Argument Preparation inactive register: Qda register: Rtp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.