[__arm_]vdupq_n_f32
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
---|---|---|---|---|---|
Helium | float32x4_t | [__arm_]vdupq_n_f32 | (float32_t a) | Vector manipulation / Create vector | |
Description Set each element of a vector register to the value of a general-purpose register. Results Qd result This intrinsic compiles to the following instructions: VDUP.32 Argument Preparation a register: Rt Architectures MVE |
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