[__arm_]veorq[_f32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float32x4_t | [__arm_]veorq[_f32] | (float32x4_t a, float32x4_t b) | Logical / Exclusive OR | |
Description Compute a bitwise EOR of a vector register with another vector register. The result is written to the destination vector register. Results Qd result This intrinsic compiles to the following instructions: VEOR Argument Preparation a register: Qnb register: Qm Architectures MVE | |||||
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