[__arm_]viwdupq_m[_n_u32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint32x4_t | [__arm_]viwdupq_m[_n_u32] | (uint32x4_t inactive, uint32_t a, uint32_t b, const int imm, mve_pred16_t p) | Vector manipulation / Create vector | |
Description Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For all variants, the updated start offset is written back to Rn. For the wrapping variant, the operation wraps so that the values written to the vector register elements are in the range [0, Rm). However, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VIWDUPT.U32 Argument Preparation inactive register: Qda register: Rnb register: Rmimm p register: Rp Architectures MVE | |||||
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