[__arm_]vld1q[_f16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float16x8_t | [__arm_]vld1q[_f16] | (float16_t const * base) | Load / Stride | |
Description Loads vector from memory, alias to vldr intrinsics where the element size of the input vector is the same as the element size being loaded from memory. Results Qd result This intrinsic compiles to the following instructions: VLDRH.16 Argument Preparation base register: Rn Architectures MVE | |||||
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