[__arm_]vld1q_z[_u32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint32x4_t | [__arm_]vld1q_z[_u32] | (uint32_t const * base, mve_pred16_t p) | Load / Stride | |
Description Loads vector from memory, alias to vldr intrinsics where the element size of the input vector is the same as the element size being loaded from memory. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VLDRWT.32 Argument Preparation base register: Rnp register: Rp Architectures MVE | |||||
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