SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint16x8x2_t[__arm_]vld2q[_u16](uint16_t const * addr)Load / Stride
Description
Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the pat parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different pat values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.
Results
Qd result.val[0]Qd2 result.val[1]
This intrinsic compiles to the following instructions:

VLD20.16 {Qd - Qd2},[Rn]

VLD21.16 {Qd - Qd2},[Rn]

Argument Preparation
addr register: Rn
Architectures
MVE