[__arm_]vldrbq_z_u8
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint8x16_t | [__arm_]vldrbq_z_u8 | (uint8_t const * base, mve_pred16_t p) | Load / Consecutive | |
Description Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. Predicated lanes are zeroed instead of retaining their previous values. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VLDRBT.8 Argument Preparation base register: Rnp register: Rp Architectures MVE | |||||
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