Intrinsics – Arm Developer

SIMD ISA	Return Type	Name	Arguments	Instruction Group
Helium	`uint32x4_t`	`[__arm_]vldrwq_gather_base_wb_z_u32`	`(uint32x4_t * addr, const int offset, mve_pred16_t p)`	Load / Gather
Description Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. Predicated lanes are zeroed instead of retaining their previous values. Results Qd resultQn addr This intrinsic compiles to the following instructions: VMSR* `P0,Rp` VPST VLDRWT.U32 `Qd,[Qn,#offset]!` Argument Preparation addr register: Qnoffset p register: Rp Architectures MVE

[__arm_]vldrwq_gather_base_wb_z_u32