SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint32_t[__arm_]vmladavq_p[_s8](int8x16_t m1, int8x16_t m2, mve_pred16_t p)Vector arithmetic / Multiply / Multiply-accumulate
Description
The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together. At the end of each beat these results are accumulated and the lower 32 bits written back to the general-purpose destination register. The initial value of the general-purpose destination register can optionally be added to the result.
Results
Rda result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VMLADAVT.S8 Rda,Qn,Qm

Argument Preparation
m1 register: Qnm2 register: Qmp register: Rp
Architectures
MVE