SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint16x8_t[__arm_]vmulltq_int_m[_s8](int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)Vector arithmetic / Multiply / Multiplication
Description
Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.
Results
Qd result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VMULLTT.S8 Qd,Qn,Qm

Argument Preparation
inactive register: Qda register: Qnb register: Qmp register: Rp
Architectures
MVE