[__arm_]vmvnq[_u32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint32x4_t | [__arm_]vmvnq[_u32] | (uint32x4_t a) | Logical / Bitwise NOT | |
Description Bitwise invert the value of a vector register and place the result in another vector register. Results Qd result This intrinsic compiles to the following instructions: VMVN Argument Preparation a register: Qm Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.