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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint16x8_t[__arm_]vmvnq_m[_n_u16](uint16x8_t inactive, const uint16_t imm, mve_pred16_t p)Logical / Bitwise NOT
Description
Set each element of a vector register to the bitwise inverse of the immediate operand value. The immediate is generated by the AdvSIMDExpandImm() function based on the requested data type and immediate value.
Results
Qd result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VMVNT.I16 Qd,#imm

Argument Preparation
inactive register: Qdimm p register: Rp
Architectures
MVE