[__arm_]vmvnq_m[_s8]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int8x16_t | [__arm_]vmvnq_m[_s8] | (int8x16_t inactive, int8x16_t a, mve_pred16_t p) | Logical / Bitwise NOT | |
Description Bitwise invert the value of a vector register and place the result in another vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VMVNT Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
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