[__arm_]vnegq[_f32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float32x4_t | [__arm_]vnegq[_f32] | (float32x4_t a) | Logical / Negate | |
Description Negate the value of each element in a vector register. Results Qd result This intrinsic compiles to the following instructions: VNEG.F32 Argument Preparation a register: Qm Architectures MVE | |||||
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