[__arm_]vnegq_m[_f32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float32x4_t | [__arm_]vnegq_m[_f32] | (float32x4_t inactive, float32x4_t a, mve_pred16_t p) | Logical / Negate | |
Description Negate the value of each element in a vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VNEGT.F32 Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.