[__arm_]vorrq_m[_s32]
SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
---|---|---|---|---|---|
Helium | int32x4_t | [__arm_]vorrq_m[_s32] | (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) | Logical / OR | |
Description Compute a bitwise OR of a vector register with another vector register. The result is written to the destination vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VORRT Argument Preparation inactive register: Qda register: Qnb register: Qmp register: Rp Architectures MVE |
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.