[__arm_]vpselq[_f32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | float32x4_t | [__arm_]vpselq[_f32] | (float32x4_t a, float32x4_t b, mve_pred16_t p) | Predication / Predicated select | |
Description Compute a bytewise conditional select of a vector register with another vector register, based on the VPR predicate bits Results Qd result This intrinsic compiles to the following instructions: VMSR VPSEL Argument Preparation a register: Qnb register: Qmp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.