[__arm_]vpselq[_s8]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int8x16_t | [__arm_]vpselq[_s8] | (int8x16_t a, int8x16_t b, mve_pred16_t p) | Predication / Predicated select | |
Description Compute a bytewise conditional select of a vector register with another vector register, based on the VPR predicate bits Results Qd result This intrinsic compiles to the following instructions: VMSR VPSEL Argument Preparation a register: Qnb register: Qmp register: Rp Architectures MVE | |||||
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