SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint32x4_t[__arm_]vqdmlsdhxq_m[_s32](int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)Vector arithmetic / Multiply / Saturating multiply-accumulate
Description
The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.
Results
Qd result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VQDMLSDHXT.S32 Qd,Qn,Qm

Argument Preparation
inactive register: Qda register: Qnb register: Qmp register: Rp
Architectures
MVE