SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumint32x4_t[__arm_]vqdmulltq_m[_s16](int32x4_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)Vector arithmetic / Multiply / Saturating multiply
Description
Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.
Results
Qd result
This intrinsic compiles to the following instructions:

VMSR P0,Rp

VPST

VQDMULLTT.S16 Qd,Qn,Qm

Argument Preparation
inactive register: Qda register: Qnb register: Qmp register: Rp
Architectures
MVE