[__arm_]vqnegq_m[_s32]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | int32x4_t | [__arm_]vqnegq_m[_s32] | (int32x4_t inactive, int32x4_t a, mve_pred16_t p) | Logical / Negate | |
Description Negate the value and saturate each element in a vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VQNEGT.S32 Argument Preparation inactive register: Qda register: Qmp register: Rp Architectures MVE | |||||
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