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SIMD ISAReturn TypeNameArgumentsInstruction Group
Heliumuint32x4_t[__arm_]vqrshlq[_n_u32](uint32x4_t a, int32_t b)Shift / Left / Vector saturating rounding shift left
Description
The vector variant shifts each element of the first vector by a value from the least significant byte of the corresponding element of the second vector and places the results in the destination vector. The register variants shift each element of a vector register by the value specified in a source register. The direction of the shift depends on the sign of the element from the second vector register.
Results
Qda result
This intrinsic compiles to the following instructions:

VQRSHL.U32 Qda,Rm

Argument Preparation
a register: Qdab register: Rm
Architectures
MVE