[__arm_]vqrshlq_m[_u16]
| SIMD ISA | Return Type | Name | Arguments | Instruction Group | |
|---|---|---|---|---|---|
| Helium | uint16x8_t | [__arm_]vqrshlq_m[_u16] | (uint16x8_t inactive, uint16x8_t a, int16x8_t b, mve_pred16_t p) | Shift / Left / Vector saturating rounding shift left | |
Description The vector variant shifts each element of the first vector by a value from the least significant byte of the corresponding element of the second vector and places the results in the destination vector. The register variants shift each element of a vector register by the value specified in a source register. The direction of the shift depends on the sign of the element from the second vector register. Results Qd result This intrinsic compiles to the following instructions: VMSR VPST VQRSHLT.U16 Argument Preparation inactive register: Qda register: Qmb register: Qnp register: Rp Architectures MVE | |||||
Copyright © 1995-2025 Arm Limited (or its affiliates). All rights reserved.